1. Field of the Invention
The present invention relates to a semiconductor chip package, more particularly, to a stacked semiconductor chip package.
2. Description of the Related Art
Referring to FIGS. 1a and 1b, the conventional stacked semiconductor chip package 1 comprises a substrate 11, a first chip 12, a plate 13, and a second chip 14. The first chip 12 adheres to the substrate 11 and electrically connects to the substrate 11 by a plurality of leads. The plate 13 is mounted between the first chip 12 and the second chip 14. The size of the plate 13 is usually smaller than that of the first cup 12 so as to avoid interfering the connection of the first chip 12 and the substrate 11,
The plate 13 adheres to the first chip 12 by using an adhesive. The second chip 14 is mounted on the plate 13, and adheres to the plate 13 by using an adhesive. Referring to FIG. 1b, because the size of the second chip 14 is larger than that of the plate 13, the testing instrument cannot detect the thickness of the adhesive layer 15 and the size of the overflow adhesive portion 16. If the adhesive layer 14 is too thin or the overflow adhesive portion 16 is too large, the adhesive on the overflow adhesive portion 16 will be broken so that the second chip 14 cannot exactly adhere to the plate 13, which will cause the semiconductor chip package product failure.
Therefore, it is necessary to provide an innovative and progressive semiconductor chip package so as to solve the above problem.